Secure, Trusted, and Assured Microelectronics (STAM) Center
The STAM Center investigates new technologies and methodologies to offer opportunities for designing secure computing devices and systems that go beyond what is currently achievable. The center couples its research mission with active recruiting and training of students, especially domestic students, targeting applications of national security importance.
The center conducts fundamental research in three technical areas meant to establish the foundation for future secure and trusted semiconductor/ microelectronics technologies: (1) new substrates, synthesis, and fabrication, (2) new computing paradigms and architectures, and (3) integrated sensing, edge computing, and secure communications.
CENTER TECHNICAL AREAS
Researchers and students at the center investigate, design and prototype application-aware processors and embedded systems with cybersecurity compliance, technology transfer and field tests readiness in mind. The team uses a multidisciplinary and integrative approach consisting of algorithmic optimization, design flow automation, hardware-firmware co-development and prototyping. The center is organized in six research laboratories – two technology laboratories (SemiSec Laboratory and LUCS), and four application laboratories (ASCS Laboratory, AITS Laboratory, CAES Laboratory, and SECPS Laboratory).
Semiconductor Security (SemiSEC) Laboratory: Zero-Trust IC Fabrication, Age-related IC Failures and Security, Supply Chain Trust Challenges, Secure-by-Construction IC Design
Laboratory for Unconventional Computing Substrates (LUCS): Approximate Computing, Cryogenics Computing, Quantum Computing, Secure Bio-Microelectronics
Private and Secure AI
Artificial Intelligence Technology and Systems (AITS) Laboratory: Privacy-Preserving AI/ML Systems Secure ML Hardware Accelerators Real-Time/Low-power ML Engines
Computer Architecture & Embedded Systems (CAES) Laboratory: Trusted Execution Environment Architecture, Enclave-Driven Architecture, Secure High-Performance Computing Architecture, Graph Processor Design.